Jumping in on the bandwidth question. For the ADS-B waveform, a logic 1 bit is transmitted as carrier on for 0.5 microsecond, carrier off for 0.5 microsecond. A logic 0 bit is the reverse, i.e. carrier off for 0.5 microsecond, carrier on for 0.5 microsecond The period of a bit (or symbol) is 1 microsecond, so the repetition rate is 1 MHz.
In the frequency domain, for a string of 1’s, (or a string of 0’s) the spectrum has lines at fc +/- 1 MHz, fc +/- 3 MHz, fc +/- 5 MHz, etc, where fc is the carrier frequency (1090 MHz). The magnitudes of the spectral lines are shaped by sin(x)/x. But the important point is the primary spectral lines are offset at +/- 1 MHz from the carrier.
It is sufficient to sample this signal at a 2 MHz sample rate – that is, in an I/Q receiver, 2 MHz on the I leg and 2 MHz on the Q leg. As a matter of fact, the original dump1090 used that sample rate.
Either an external reference (if there is any point - I don’t think there is for this application) or just use the clock of one of the V3’s to drive the others.
The V3 and V4 have Clk_Out as well as Clk_In for exactly this purpose.
Do you have a link to where that picture came from, or is it your own? I didn’t know you could chain the clocks like that on RTL-SDR dongles. How many clocks can one device drive?
Looks like I would have to solder those connections. With my shaky hands, I wouldn’t feel confident enough to solder a 1/4 watt resistor, let alone the small components on circuit boards these days. I can still screw on a connector however (more or less). Just an observation.
It’s five rtlsdrs in a trenchcoat (plus I think maybe some reference signal generation so you can align the dongles with each other? I’m not sure. And probably an internal USB hub). So each receiver has the usual rtlsdr characteristics (8 bit ADC etc)
USB bus bandwidth is probably an issue if you tried to do the same with the airspy, you’d need to get them onto separate USB buses somehow
Sure - it’s not mine, but straight off RTL-Blogs site (scroll down to page 7)
The example shown has them daisy-chained, so each is only driving one other. Depending on the input impedance, you’d probably get away with two and quite possible four in star configuration before need needing to buffer the clock.
Yeah - none of us are getting younger. I do my SMD work under a microscope to get good results.
Seems like something that would be useful for a general purpose coherent receiver is somewhere between two to four RTL-SDR devices in a box wired up for a common freq reference. Also possibly a USB hub and power supply. Less than a krakensdr but more general purpose like @geckoVN suggested above.
I was thinking about a krakensdr. I actually had the page book marked from over a year ago. I must have been looking at it back then. But I already have four BladeSDR so might as well use those.
I think with the bladeSDR you get about 80-MSPS per USB bus. That is shared between channels so you can only really get about 40-MSPS out of two RX. That is with USB 3.x speeds. But with a low sampling speed like 2-MSPS or whatever you can squeeze in a lot more obviously. It’s also shared with the TX.
However, if I recall correctly, you can use 8-bit instead of 16-bit which would half the USB bandwidth required. I think it’s always had that. I could have sworn it always had that. But recently they added where you can get somewhere over 100-MSPS. I forget the word they used to describe what they did to the chip to make it do it.
But boy you got to be able to handle that much data, haha. I can only imagine trying to process it all in software. I’m going to have to move to an FPGA solution. If anyone knows of any FPGA boards that are license free that would be perfect. I got one board I accidentally bought but it requires a license of about $1000 USD a year to program. Oopps.. haha.
Edit: Just to be clear: There are many people who run stream1090 on a raspberrpi, piping in 10 Mio IQ pairs per second, each leg is filtered. Then the magnitude is being upsampled to 24 Mio mags per second. I do not have the numbers for the 10 Msps input, for 6 Msps to 24 Msps upsampling speed, the cpu usage on a RP5 is below 20%. I do not see any problem here with running 40 or more without filters in a 1:1 config.
The library for the BladeSDR gives a warning when your combined total, across all RX and TX channels, exceeds 80-MSPS. It is supposedly the maximum reliable throughput supported over USB 3. So, if you had two RX channels you could run each at 40-MSPS for a combined total of 80-MSPS.
There is math here and i am already lost. But there is also some smell of assumption in the air.
This assumes that you know where a bit starts. And this is not the case. You can now play both scenarios: Preamble detection or the stream1090 way. Your not-bit rate but symbol rate is 2 MHz which requires 4 MHz.
Are you talking about beamforming? The reason I say that is because the work required increases when forming beams. You have the LMS beamformer on one hand which homes in on the weights but on the other hand if you want 40 explicit beams you’re going to end up doing the decoding 40 times and that consumes a lot of extra CPU time.
That is why I want to move into the FPGA where I can have… I’m just going to throw out a number because I don’t know how many resources it would take but let’s say 40 beams simultaneously formed and demodulated. I’d hope I could do say 300 or 600 beams, but I just don’t know because it depends on the size of the FPGA.
I think you need to re-read what jim is saying: most of the signal’s energy is contained within +/-1MHz around the carrier, i.e. capturing 2MHz of signal bandwidth is sufficient (more is obviously better, but 2MHz is probably the minimum). You can capture 2MHz of bandwidth with 2Msps complex samples (effectively, 4Msps real samples).
The “+/-1MHz” part comes from treating an ADS-B signal something like amplitude-modulating a 1090MHz carrier with a 1MHz square wave, which is a reasonable approximation.
